Filter
Top Products
Vol. 2A 1-3
ABOUT THIS MANUAL
Chapter 1 — About This Manual. Gives an overview of all five volumes of the
Intel
®
64 and IA-32 Architectures Software Developer’s Manual. It also describes the
notational conventions in these manuals and lists related Intel
®
manuals and docu-
mentation of interest to programmers and hardware designers.
Chapter 2 — Instruction Format. Describes the machine-level instruction format
used for all IA-32 instructions and gives the allowable encodings of prefixes, the
operand-identifier byte (ModR/M byte), the addressing-mode specifier byte (SIB
byte), and the displacement and immediate bytes.
Chapter 3 — Instruction Set Reference, A-M. Describes Intel 64 and IA-32
instructions in detail, including an algorithmic description of operations, the effect on
flags, the effect of operand- and address-size attributes, and the exceptions that
may be generated. The instructions are arranged in alphabetical order. General-
purpose, x87 FPU, Intel MMX™ technology, SSE/SSE2/SSE3 extensions, and system
instructions are included.
Chapter 4 — Instruction Set Reference, N-Z. Continues the description of Intel
64 and IA-32 instructions started in Chapter 3. It provides the balance of the alpha-
betized list of instructions and starts Intel
®
64 and IA-32 Architectures Software
Developer’s Manual, Volume 2B.
Chapter 5 — VMX Instruction Reference. Describes the virtual-machine exten-
sions (VMX). VMX is intended for a system executive to support virtualization of
processor hardware and a system software layer acting as a host to multiple guest
software environments.
Chapter 6— Safer Mode Extensions Reference. Describes the safer mode exten-
sions (SMX). SMX is intended for a system executive to support launching a
measured environment in a platform where the identity of the software controlling
the platform hardware can be measured for the purpose of making trust decisions.
Appendix A — Opcode Map. Gives an opcode map for the IA-32 instruction set.
Appendix B — Instruction Formats and Encodings. Gives the binary encoding of
each form of each IA-32 instruction.
Appendix C — Intel
®
C/C++ Compiler Intrinsics and Functional Equivalents.
Lists the Intel
®
C/C++ compiler intrinsics and their assembly code equivalents for each
of the IA-32 MMX and SSE/SSE2/SSE3 instructions.
1.3 NOTATIONAL CONVENTIONS
This manual uses specific notation for data-structure formats, for symbolic represen-
tation of instructions, and for hexadecimal and binary numbers. A review of this
notation makes the manual easier to read.