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3-608 Vol. 2A MOV—Move to/from Debug Registers
INSTRUCTION SET REFERENCE, A-M
MOV—Move to/from Debug Registers
Description
Moves the contents of a debug register (DR0, DR1, DR2, DR3, DR4, DR5, DR6, or
DR7) to a general-purpose register or vice versa. The operand size for these instruc-
tions is always 32 bits in non-64-bit modes, regardless of the operand-size attribute.
(See Chapter 18, “Debugging and Performance Monitoring”, of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3A, for a detailed descrip-
tion of the flags and fields in the debug registers.)
The instructions must be executed at privilege level 0 or in real-address mode.
When the debug extension (DE) flag in register CR4 is clear, these instructions
operate on debug registers in a manner that is compatible with Intel386 and Intel486
processors. In this mode, references to DR4 and DR5 refer to DR6 and DR7, respec-
tively. When the DE flag in CR4 is set, attempts to reference DR4 and DR5 result in
an undefined opcode (#UD) exception. (The CR4 register was added to the IA-32
Architecture beginning with the Pentium processor.)
At the opcode level, the reg field within the ModR/M byte specifies which of the debug
registers is loaded or read. The two bits in the mod field are always 11. The r/m field
specifies the general-purpose register loaded or read.
In 64-bit mode, the instruction’s default operation size is 64 bits. Use of the REX.B
prefix permits access to additional registers (R8-R15). Use of the REX.W or 66H
prefix is ignored. See the summary chart at the beginning of this section for encoding
data and limits.
Operation
IF ((DE = 1) and (SRC or DEST = DR4 or DR5))
THEN
#UD;
ELSE
DEST ← SRC;
FI;
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
0F 21/r MOV r32, DR0-DR7 N.E. Valid Move debug register to r32
0F 21/r MOV r64, DR0-DR7 Valid N.E. Move extended debug register
to r64.
0F 23 /r MOV DR0-DR7, r32 N.E. Valid Move r32 to debug register
0F 23 /r MOV DR0-DR7, r64 Valid N.E. Move r64 to extended debug
register.