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Vol. 2A 3-473
INSTRUCTION SET REFERENCE, A-M
INT n/INTO/INT 3—Call to Interrupt Procedure
When the processor is executing in virtual-8086 mode, the IOPL determines the
action of the INT n instruction. If the IOPL is less than 3, the processor generates a
#GP(selector) exception; if the IOPL is 3, the processor executes a protected mode
interrupt to privilege level 0. The interrupt gate's DPL must be set to 3 and the target
CPL of the interrupt handler procedure must be 0 to execute the protected mode
interrupt to privilege level 0.
The interrupt descriptor table register (IDTR) specifies the base linear address and
limit of the IDT. The initial base address value of the IDTR after the processor is
powered up or reset is 0.
Operation
The following operational description applies not only to the INT n and INTO instruc-
tions, but also to external interrupts and exceptions.
IF PE = 0
THEN
GOTO REAL-ADDRESS-MODE;
ELSE (* PE
= 1 *)
IF (VM
= 1 and IOPL < 3 AND INT n)
THEN
#GP(0);
ELSE (* Protected mode, IA-32e mode, or virtual-8086 mode interrupt *)
IF (IA32_EFER.LMA
= 0)
THEN (* Protected mode, or virtual-8086 mode interrupt *)
GOTO PROTECTED-MODE;
ELSE (* IA-32e mode interrupt *)
GOTO IA-32e-MODE;
FI;
FI;
FI;
REAL-ADDRESS-MODE:
IF ((vector_number ∗ 4) + 3) is not within IDT limit
THEN #GP; FI;
IF stack not large enough for a 6-byte return information
THEN #SS; FI;
Push (EFLAGS[15:0]);
IF ← 0; (* Clear interrupt flag *)
TF ← 0; (* Clear trap flag *)
AC ← 0; (* Clear AC flag *)
Push(CS);
Push(IP);
(* No error codes are pushed *)