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3-246 Vol. 2A CVTTPS2PI—Convert with Truncation Packed Single-Precision Floating-Point Values to
Packed Doubleword Integers
INSTRUCTION SET REFERENCE, A-M
CVTTPS2PI—Convert with Truncation Packed Single-Precision
Floating-Point Values to Packed Doubleword Integers
Description
Converts two packed single-precision floating-point values in the source operand
(second operand) to two packed signed doubleword integers in the destination
operand (first operand). The source operand can be an XMM register or a 64-bit
memory location. The destination operand is an MMX technology register. When the
source operand is an XMM register, the two single-precision floating-point values are
contained in the low quadword of the register.
When a conversion is inexact, a truncated (round toward zero) result is returned. If a
converted result is larger than the maximum signed doubleword integer, the floating-
point invalid exception is raised, and if this exception is masked, the indefinite
integer value (80000000H) is returned.
This instruction causes a transition from x87 FPU to MMX technology operation (that
is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all
0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is
pending, the exception is handled before the CVTTPS2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
DEST[63:32] ← Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTTPS2PI __m64 _mm_cvttps_pi32(__m128 a)
SIMD Floating-Point Exceptions
Invalid, Precision.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
0F 2C /r CVTTPS2PI mm,
xmm/m64
Valid Valid Convert two single-precision floating-
point values from xmm/m64 to two
signed doubleword signed integers in mm
using truncation.