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Vol. 2A 3-39
INSTRUCTION SET REFERENCE, A-M
ADDSD—Add Scalar Double-Precision Floating-Point Values
ADDSD—Add Scalar Double-Precision Floating-Point Values
Description
Adds the low double-precision floating-point values from the source operand (second
operand) and the destination operand (first operand), and stores the double-preci-
sion floating-point result in the destination operand.
The source operand can be an XMM register or a 64-bit memory location. The desti-
nation operand is an XMM register. The high quadword of the destination operand
remains unchanged. See Chapter 11 in the Intel® 64 and IA-32 Architectures Soft-
ware Developer’s Manual, Volume 1, for an overview of a scalar double-precision
floating-point operation.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Operation
DEST[63:0] ← DEST[63:0] + SRC[63:0];
(* DEST[127:64] unchanged *)
Intel C/C++ Compiler Intrinsic Equivalent
ADDSD __m128d _mm_add_sd (m128d a, m128d b)
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
#NM If CR0.TS[bit 3] = 1.
#XM If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 1.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
F2 0F 58 /r ADDSD xmm1, xmm2/m64 Valid Valid Add the low double-
precision floating-point
value from xmm2/m64 to
xmm1.