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Vol. 2A 3-711
INSTRUCTION SET REFERENCE, A-M
MWAIT—Monitor Wait
processor will exit the state and handle the interrupt. If an SMI caused the processor
to exit the implementation-dependent-optimized state, execution will resume at the
instruction following MWAIT after handling of the SMI. Unlike the HLT instruction, the
MWAIT instruction does not support a restart at the MWAIT instruction. There may
also be other implementation-dependent events or time-outs that may take the
processor out of the implementation-dependent-optimized state and resume execu-
tion at the instruction following the MWAIT.
If the preceding MONITOR instruction did not successfully arm an address range or if
the MONITOR instruction has not been executed prior to executing MWAIT, then the
processor will not enter the implementation-dependent-optimized state. Execution
will resume at the instruction following the MWAIT.
MWAIT for Power Management
MWAIT accepts a hint and optional extension to the processor that it can enter a
specified target C state while waiting for an event or a store operation to the address
range armed by MONITOR. Support for MWAIT extensions for power management is
indicated by CPUID.05H.ECX[0] reporting 1.
EAX and ECX will be used to communicate the additional information to the MWAIT
instruction, such as the kind of optimized state the processor should enter. ECX spec-
ifies optional extensions for the MWAIT instruction. EAX may contain hints such as
the preferred optimized state the processor should enter. A given processor imple-
mentation may choose to ignore the hint and continue executing the next instruction.
Future processor implementations may implement several optimized “waiting” states
and will select among those states based on the hint argument.
Table 3-62 describes the meaning of ECX and EAX registers for MWAIT extensions.
Table 3-62. MWAIT Extension Register (ECX)
Bits Description
0 Treat Interrupt as break-event, even when interrupts are disabled
(EFLAGS.IF=0)
31: 1 Reserved