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3-178 Vol. 2A CPUID—CPU Identification
INSTRUCTION SET REFERENCE, A-M
Table 3-17. Encoding of Cache and TLB Descriptors
Descriptor Value Cache or TLB Description
00H Null descriptor
01H Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries
02H Instruction TLB: 4 MByte pages, 4-way set associative, 2 entries
03H Data TLB: 4 KByte pages, 4-way set associative, 64 entries
04H Data TLB: 4 MByte pages, 4-way set associative, 8 entries
05H Data TLB1: 4 MByte pages, 4-way set associative, 32 entries
06H 1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size
08H 1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size
0AH 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size
0BH Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries
0CH 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size
22H 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines
per sector
23H 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per
sector
25H 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per
sector
29H 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per
sector
2CH 1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size
30H 1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size
40H No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-
level cache
41H 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size
42H 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size
43H 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size
44H 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size
45H 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size
46H 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size
47H 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size
49H 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size
50H Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries
51H Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries
52H Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries