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Vol. 2A 3-5
INSTRUCTION SET REFERENCE, A-M
• r/m32 — A doubleword general-purpose register or memory operand used for
instructions whose operand-size attribute is 32 bits. The doubleword general-
purpose registers are: EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI. The contents of
memory are found at the address provided by the effective address computation.
Doubleword registers R8D - R15D are available when using REX.R in 64-bit
mode.
• r/m64 — A quadword general-purpose register or memory operand used for
instructions whose operand-size attribute is 64 bits when using REX.W.
Quadword general-purpose registers are: RAX, RBX, RCX, RDX, RDI, RSI, RBP,
RSP, R8–R15; these are available only in 64-bit mode. The contents of memory
are found at the address provided by the effective address computation.
• m — A 16-, 32- or 64-bit operand in memory.
• m8 — A byte operand in memory, usually expressed as a variable or array name,
but pointed to by the DS:(E)SI or ES:(E)DI registers. In 64-bit mode, it is pointed
to by the RSI or RDI registers.
• m16 — A word operand in memory, usually expressed as a variable or array
name, but pointed to by the DS:(E)SI or ES:(E)DI registers. This nomenclature is
used only with the string instructions.
• m32 — A doubleword operand in memory, usually expressed as a variable or
array name, but pointed to by the DS:(E)SI or ES:(E)DI registers. This nomen-
clature is used only with the string instructions.
• m64 — A memory quadword operand in memory.
• m128 — A memory double quadword operand in memory. This nomenclature is
used only with SSE and SSE2 instructions.
• m16:16, m16:32 & m16:64 — A memory operand containing a far pointer
composed of two numbers. The number to the left of the colon corresponds to the
pointer's segment selector. The number to the right corresponds to its offset.
• m16&32, m16&16, m32&32, m16&64 — A memory operand consisting of
data item pairs whose sizes are indicated on the left and the right side of the
ampersand. All memory addressing modes are allowed. The m16&16 and
m32&32 operands are used by the BOUND instruction to provide an operand
containing an upper and lower bounds for array indices. The m16&32 operand is
used by LIDT and LGDT to provide a word with which to load the limit field, and a
doubleword with which to load the base field of the corresponding GDTR and
IDTR registers. The m16&64 operand is used by LIDT and LGDT in 64-bit mode to
provide a word with which to load the limit field, and a quadword with which to
load the base field of the corresponding GDTR and IDTR registers.
• moffs8, moffs16, moffs32, moffs64 — A simple memory variable (memory
offset) of type byte, word, or doubleword used by some variants of the MOV
instruction. The actual address is given by a simple offset relative to the segment
base. No ModR/M byte is used in the instruction. The number shown with moffs
indicates its size, which is determined by the address-size attribute of the
instruction.