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3-568 Vol. 2A MASKMOVQ—Store Selected Bytes of Quadword
INSTRUCTION SET REFERENCE, A-M
MASKMOVQ—Store Selected Bytes of Quadword
Description
Stores selected bytes from the source operand (first operand) into a 64-bit memory
location. The mask operand (second operand) selects which bytes from the source
operand are written to memory. The source and mask operands are MMX technology
registers. The location of the first byte of the memory location is specified by DI/EDI
and DS registers. (The size of the store address depends on the address-size
attribute.)
The most significant bit in each byte of the mask operand determines whether the
corresponding byte in the source operand is written to the corresponding byte loca-
tion in memory: 0 indicates no write and 1 indicates write.
The MASKMOVQ instruction generates a non-temporal hint to the processor to mini-
mize cache pollution. The non-temporal hint is implemented by using a write
combining (WC) memory type protocol (see “Caching of Temporal vs. Non-Temporal
Data” in Chapter 10, of the Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 1). Because the WC protocol uses a weakly-ordered memory consis-
tency model, a fencing operation implemented with the SFENCE or MFENCE instruc-
tion should be used in conjunction with MASKMOVEDQU instructions if multiple
processors might use different memory types to read/write the destination memory
locations.
This instruction causes a transition from x87 FPU to MMX technology state (that is,
the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s
[valid]).
The behavior of the MASKMOVQ instruction with a mask of all 0s is as follows:
• No data will be written to memory.
• Transition from x87 FPU to MMX technology state will occur.
• Exceptions associated with addressing memory and page faults may still be
signaled (implementation dependent).
• Signaling of breakpoints (code or data) is not guaranteed (implementation
dependent).
• If the destination memory region is mapped as UC or WP, enforcement of
associated semantics for these memory types is not guaranteed (that is, is
reserved) and is implementation-specific.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
0F F7 /r MASKMOVQ mm1,
mm2
Valid Valid Selectively write bytes from mm1 to
memory location using the byte mask in
mm2. The default memory location is
specified by DS:EDI.