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3-552 Vol. 2A LODS/LODSB/LODSW/LODSD/LODSQ—Load String
INSTRUCTION SET REFERENCE, A-M
correct location. The location is always specified by the DS:(E)SI registers, which
must be loaded correctly before the load string instruction is executed.
The no-operands form provides “short forms” of the byte, word, and doubleword
versions of the LODS instructions. Here also DS:(E)SI is assumed to be the source
operand and the AL, AX, or EAX register is assumed to be the destination operand.
The size of the source and destination operands is selected with the mnemonic:
LODSB (byte loaded into register AL), LODSW (word loaded into AX), or LODSD
(doubleword loaded into EAX).
After the byte, word, or doubleword is transferred from the memory location into the
AL, AX, or EAX register, the (E)SI register is incremented or decremented automati-
cally according to the setting of the DF flag in the EFLAGS register. (If the DF flag is
0, the (E)SI register is incremented; if the DF flag is 1, the ESI register is decre-
mented.) The (E)SI register is incremented or decremented by 1 for byte operations,
by 2 for word operations, or by 4 for doubleword operations.
In 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. LODS/LODSQ
load the quadword at address (R)SI into RAX. The (R)SI register is then incremented
or decremented automatically according to the setting of the DF flag in the EFLAGS
register.
The LODS, LODSB, LODSW, and LODSD instructions can be preceded by the REP
prefix for block loads of ECX bytes, words, or doublewords. More often, however,
these instructions are used within a LOOP construct because further processing of
the data moved into the register is usually necessary before the next transfer can be
made. See “REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix” in
Chapter 4, Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume
2B, for a description of the REP prefix.
Operation
IF AL ← SRC; (* Byte load *)
THEN AL ← SRC; (* Byte load *)
IF DF
= 0
THEN (E)SI ← (E)SI + 1;
ELSE (E)SI ← (E)SI – 1;
FI;
ELSE IF AX ← SRC; (* Word load *)
THEN IF DF
= 0
THEN (E)SI ← (E)SI + 2;
ELSE (E)SI ← (E)SI – 2;
IF;
FI;
ELSE IF EAX ← SRC; (* Doubleword load *)
THEN IF DF
= 0
THEN (E)SI ← (E)SI + 4;
ELSE (E)SI ← (E)SI – 4;