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Rev. 1.00, 05/04, page 72 of 544
5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL)
The ISCR registers select the source that generates an interrupt request at pins IRQ7 to IRQ0.
• ISCRH
Bit Bit Name
Initial
Value
R/W Description
7
6
IRQ7SCB
IRQ7SCA
0
0
R/W
R/W
5
4
IRQ6SCB
IRQ6SCA
0
0
R/W
R/W
3
2
IRQ5SCB
IRQ5SCA
0
0
R/W
R/W
1
0
IRQ4SCB
IRQ4SCA
0
0
R/W
R/W
IRQn Sense Control B
IRQn Sense Control A
00: Interrupt request generated at low level of IRQn
input
01: Interrupt request generated at falling edge of IRQn
input
10: Interrupt request generated at rising edge of IRQn
input
11: Interrupt request generated at both falling and
rising edges of IRQn input
(n = 7 to 4)
• ISCRL
Bit Bit Name
Initial
Value R/W Description
7
6
IRQ3SCB
IRQ3SCA
0
0
R/W
R/W
5
4
IRQ2SCB
IRQ2SCA
0
0
R/W
R/W
3
2
IRQ1SCB
IRQ1SCA
0
0
R/W
R/W
1
0
IRQ0SCB
IRQ0SCA
0
0
R/W
R/W
IRQn Sense Control B
IRQn Sense Control A
00: Interrupt request generated at low level of IRQn
input
01: Interrupt request generated at falling edge of IRQn
input
10: Interrupt request generated at rising edge of IRQn
input
11: Interrupt request generated at both falling and
rising edges of IRQn input
(n = 3 to 0)