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Rev. 1.00, 05/04, page xxvi of xxxiv
Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception ..............270
Figure 12.21 Sample Flowchart for Mode Transition during Transmission...............................274
Figure 12.22 Pin States during Transmission in Asynchronous Mode (Internal Clock) ............ 274
Figure 12.23 Pin States during Transmission in Clocked Synchronous Mode
(Internal Clock).....................................................................................................275
Figure 12.24 Sample Flowchart for Mode Transition during Reception....................................275
Figure 12.25 Switching from SCK Pins to Port Pins..................................................................276
Figure 12.26 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins..........276
Section 13 I2C Bus Interface (IIC)
Figure 13.1 Block Diagram of I
2
C Bus Interface .......................................................................278
Figure 13.2 I
2
C Bus Interface Connections (Example: This LSI as Master)..............................279
Figure 13.3 I
2
C Bus Data Format (I
2
C Bus Format)...................................................................307
Figure 13.4 I
2
C Bus Data Format (Serial Format)......................................................................307
Figure 13.5 I
2
C Bus Timing........................................................................................................308
Figure 13.6 Sample Flowchart for IIC Initialization ..................................................................309
Figure 13.7 Sample Flowchart for Operations in Master Transmit Mode..................................310
Figure 13.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0) ......312
Figure 13.9 Example of Stop Condition Issuance Operation Timing
in Master Transmit Mode (MLS = WAIT = 0).......................................................313
Figure 13.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1).............314
Figure 13.11 Example of Operation Timing in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)............................................................................316
Figure 13.12 Example of Stop Condition Issuance Operation Timing
in Master Receive Mode (MLS = WAIT = 0, HNDS = 1) ...................................316
Figure 13.13 Sample Flowchart for Operations in Master Receive Mode
(receiving multiple bytes) (WAIT = 1).................................................................317
Figure 13.14 Sample Flowchart for Operations in Master Receive Mode
(receiving a single byte) (WAIT = 1) ...................................................................318
Figure 13.15 Example of Master Receive Mode Operation Timing
(MLS = ACKB = 0, WAIT = 1) ...........................................................................320
Figure 13.16 Example of Stop Condition Issuance Timing in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1) ...........................................................................321
Figure 13.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1)...............322
Figure 13.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1) ...324
Figure 13.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1) ...324
Figure 13.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)...............325
Figure 13.21 Example of Slave Receive Mode Operation Timing (1)
(MLS = ACKB = 0, HNDS = 0)...........................................................................327
Figure 13.22 Example of Slave Receive Mode Operation Timing (2)
(MLS = ACKB = 0, HNDS = 0)...........................................................................327
Figure 13.23 Sample Flowchart for Slave Transmit Mode.........................................................328
Figure 13.24 Example of Slave Transmit Mode Operation Timing (MLS = 0) .........................330