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Rev. 1.00, 05/04, page 384 of 544
• STR3 (TWRE = 1 or SELSTR3 = 0)
R/W
Bit Bit Name
Initial
Value Slave Host
Description
7 IBF3B 0 R R Bidirectional Data Register Input Buffer Full
Set to 1 when the host processor writes to TWR15. This
is an internal interrupt source to the slave processor (this
LSI). IBF3B is cleared to 0 when the slave processor
reads TWR15.
0: [Clearing condition]
When the slave processor reads TWR15
1: [Setting condition]
When the host processor writes to TWR15 using I/O
write cycle
6 OBF3B 0 R/(W)* R Bidirectional Data Register Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
TWR15. OBF3B is cleared to 0 when the host processor
reads TWR15.
0: [Clearing condition]
When the host processor reads TWR15 using I/O
read cycle, or the slave processor writes 0 to the
OBF3B bit
1: [Setting condition]
When the slave processor writes to TWR15
5 MWMF 0 R R Master Write Mode Flag
Set to 1 when the host processor writes to TWR0.
MWMF is cleared to 0 when the slave processor (this
LSI) reads TWR15.
0: [Clearing condition]
When the slave processor reads TWR15
1: [Setting condition]
When the host processor writes to TWR0 using I/O
write cycle while SWMF = 0
4 SWMF 0 R/(W)* R Slave Write Mode Flag
Set to 1 when the slave processor (this LSI) writes to
TWR0. In the event of simultaneous writes by the master
and the slave, the master write has priority. SWMF is
cleared to 0 when the host reads TWR15
0: [Clearing condition]
When the host processor reads TWR15 using I/O
read cycle, or the slave processor writes 0 to the
SWMF bit
1: [Setting condition]
When the slave processor writes to TWR0 while
MWMF = 0