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Rev. 1.00, 05/04, page 326 of 544
The reception procedure and operations in slave receive are described below.
1. Initialize the IIC as described in section 13.4.2, Initialization.
Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB bits
to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception.
2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear
the IRIC flag to 0.
3. When the start condition output by the master device is detected, the BBSY flag in ICCR is set
to 1. The master device then outputs the 7-bit slave address and transmit/receive direction
(R/W) in synchronization with the transmit clock pulses.
4. When the slave address matches in the first frame following the start condition, the device
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit remains cleared to 0, and slave transmit operation is performed. When the slave
address does not match, receive operation is halted until the next start condition is detected.
5. At the 9th clock pulse of the receive frame, the slave device returns the data in the ACKB bit
as an acknowledge signal.
6. At the rise of the 9th clock pulse, the IRIC flag is set to 1. If the IEIC bit has been set to 1, an
interrupt request is sent to the CPU.
If the AASX bit has been set to 1, the IRTR flag is also set to 1.
7. At the rise of the 9th clock pulse, the receive data is transferred from ICDRS to ICDRR,
setting the ICDRF flag to 1.
8. Confirm that the STOP bit is cleared to 0 and clear the ICIC flag to 0.
9. If the next read data is the third last receive frame, wait for at least one frame time to set the
ACKB bit. Set the ACKB bit after the rise of the 9th clock pulse of the second last receive
frame.
10. Confirm that the ICDRF flag is set to 1 and read ICDR. This clears the ICDRF flag to 0.
11. At the rise of the 9th clock pulse or when the receive data is transferred from IRDRS to
ICDRR due to ICDR read operation, the IRIC and ICDRF flags are set to 1.
12. When the stop condition is detected (SDA is changed from low to high when SCL is high), the
BBSY flag is cleared to 0 and the STOP or ESTP flag is set to 1. If the STOPIM bit has been
cleared to 0, the IRIC flag is set to 1. In this case, execute step [14] to read the last receive
data.
13. Clear the IRIC flag to 0.
Receive operations can be performed continuously by repeating steps [9] to [13].
14. Confirm that the ICDRF flag is set to 1, and read ICDR.
15. Clear the IRIC flag.