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Rev. 1.00, 05/04, page xxiii of xxxiv
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram.................................................................................................2
Figure 1.2 Pin Arrangement............................................................................................................3
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode).....................................................................17
Figure 2.2 Stack Structure in Normal Mode.................................................................................17
Figure 2.3 Exception Vector Table (Advanced Mode).................................................................18
Figure 2.4 Stack Structure in Advanced Mode.............................................................................19
Figure 2.5 Memory Map...............................................................................................................20
Figure 2.6 CPU Internal Registers................................................................................................21
Figure 2.7 Usage of General Registers.........................................................................................22
Figure 2.8 Stack............................................................................................................................23
Figure 2.9 General Register Data Formats (1)..............................................................................26
Figure 2.9 General Register Data Formats (2)..............................................................................27
Figure 2.10 Memory Data Formats...............................................................................................28
Figure 2.11 Instruction Formats (Examples)................................................................................39
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode......................43
Figure 2.13 State Transitions........................................................................................................47
Section 3 MCU Operating Modes
Figure 3.1 Address Map for H8S/2111B-B..................................................................................57
Figure 3.2 Address Map for H8S/2111B-C..................................................................................58
Section 4 Exception Handling
Figure 4.1 Reset Sequence (Mode 3)............................................................................................61
Figure 4.2 Stack Status after Exception Handling........................................................................64
Figure 4.3 Operation when SP Value is Odd................................................................................65
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller........................................................................68
Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0,
Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA, and WUEMRB.....75
Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0................................................................76
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0.......81
Figure 5.5 State Transition in Interrupt Control Mode 1..............................................................82
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1.....84
Figure 5.7 Interrupt Exception Handling......................................................................................85
Figure 5.8 Address Break Block Diagram....................................................................................87
Figure 5.9 Address Break Timing Example .................................................................................89
Figure 5.10 Conflict between Interrupt Generation and Disabling...............................................90