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Rev. 1.00, 05/04, page 532 of 544
22.7.3 On-Chip Peripheral Module Timing
The on-chip peripheral module timings are shown below.
φ
Ports 1 to 9, and A to G
(read)
T
2
T
1
t
PWD
t
PRH
t
PRS
Ports 1 to 6, 8, 9,
and A to G
(write)
Figure 22.10 I/O Port Input/Output Timing
φ
t
FTIS
t
FTOD
FTOA, FTOB
FTIA, FTIB,
FTIC, FTID
Figure 22.11 FRT Input/Output Timing
φ
t
FTCS
FTCI
t
FTCWH
t
FTCWL
Figure 22.12 FRT Clock Input Timing