Filter
Top Products
Rev. 1.00, 05/04, page 110 of 544
7.5 Port 5
Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI_1 extended I/O pins, and the IIC_0 I/O
pin. P52 and ExSCK1 are NMOS push-pull outputs, and SCL0 is an NMOS open-drain output.
Port 5 has the following registers.
• Port 5 data direction register (P5DDR)
• Port 5 data register (P5DR)
7.5.1 Port 5 Data Direction Register (P5DDR)
P5DDR specifies input or output for the pins of port 5 on a bit-by-bit basis.
Bit Bit Name
Initial
Value R/W Description
7 to 3 — All 1 — Reserved
The initial value should not be changed.
2 P52DDR 0 W
1 P51DDR 0 W
0 P50DDR 0 W
The corresponding port 5 pins are output ports when
P5DDR bits are set to 1, and input ports when cleared
to 0. As SCI_1 is initialized in software standby mode,
the pin states are determined by the specifications of
ICCR, PGCTL, P5DDR, and P5DR in IIC_0.
7.5.2 Port 5 Data Register (P5DR)
P5DR stores output data for port 5 pins.
Bit Bit Name
Initial
Value R/W Description
7 to 3 — All 1 — Reserved
The initial value should not be changed.
2 P52DR 0 R/W
1 P51DR 0 R/W
0 P50DR 0 R/W
If a port 5 read is performed while P5DDR bits are set
to 1, the P5DR values are read directly, regardless of
the actual pin states. If a port 5 read is performed while
P5DDR bits are cleared to 0, the pin states are read.