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Rev. 1.00, 05/04, page 390 of 544
R/W
Bit Bit Name
Initial
Value
Slave Host Description
0 IRQ1E1 0 R/W — Host IRQ1 Interrupt Enable 1
Enables or disables a host IRQ1 interrupt request when
OBF1 is set by an ODR1 write.
0: Host IRQ1 interrupt request by OBF1 and IRQ1E1 is
disabled
[Clearing conditions]
• Writing 0 to IRQ1E1
• LPC hardware reset, LPC software reset
• Clearing OBF1 to 0
1: Host IRQ1 interrupt request by setting OBF1 to 1 is
enabled
[Setting condition]
• Writing 1 after reading IRQ1E1 = 0
• SIRQCR1
R/W
Bit Bit Name
Initial
Value
Slave Host Description
7 IRQ11E3 0 R/W — Host IRQ11 Interrupt Enable 3
Enables or disables a host IRQ11 interrupt request
when OBF3A is set by an ODR3 write.
0: Host IRQ11 interrupt request by OBF3A and
IRQ11E3 is disabled
[Clearing conditions]
• Writing 0 to IRQ11E3
• LPC hardware reset, LPC software reset
• Clearing OBF3A to 0 (when IEDIR = 0)
1: [When IEDIR = 0]
Host IRQ11 interrupt request by setting OBF3A to 1
is enabled
[When IEDIR = 1]
Host IRQ11 interrupt is requested.
[Setting condition]
• Writing 1 after reading IRQ11E3 = 0