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Rev. 1.00, 05/04, page 216 of 544
10.10 Usage Notes
10.10.1 Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T
2
state of a TCNT write cycle as shown in figure
10.14, clearing takes priority and the counter write is not performed.
φ
Address TCNT address
Internal write signal
Counter clear signal
TCNT
Note: * TMR_A, TMR_B
N
H'00
T
1
T
2
T
3
*
TCNT write cycle by CPU
Figure 10.14 Conflict between TCNT Write and Clear
10.10.2 Conflict between TCNT Write and Count-Up
If a count-up occurs during the T
2
state of a TCNT write cycle as shown in figure 10.15, the
counter write takes priority and the counter is not incremented.
Note: * TMR_A, TMR_B
T
1
T
2
T
3
*
φ
Address TCNT address
Internal write signal
TCNT input clock
TCNT N M
TCNT write cycle by CPU
Counter write data
Figure 10.15 Conflict between TCNT Write and Count-Up