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Rev. 1.00, 05/04, page 497 of 544
21.3 Register States in Each Operating Mode
Register
Abbrevia-
tion Reset
High-Speed/
Medium-
Speed Watch Sleep
Sub-
Active Sub-Sleep
Module
Stop
Software
Standby
Hardware
Standby Module
TCR_B Initialized Initialized
TCR_A Initialized Initialized
TCSR_B Initialized Initialized
TCSR_A Initialized Initialized
TCORA_B Initialized Initialized
TCORA_A Initialized Initialized
TCORB_B Initialized Initialized
TCORB_A Initialized Initialized
TCNT_B Initialized Initialized
TCNT_A Initialized Initialized
TISR_B Initialized Initialized
TICRR_A Initialized Initialized
TICRF_A Initialized Initialized
TCRAB Initialized Initialized
TMR_A
TMR_B
TCRXY* Initialized Initialized TMR_X,
TMR_Y
SPSR* Initialized Initialized SCI_1
PGCTL* Initialized Initialized IIC common
PGNOCR Initialized — — — — — — — Initialized
PENOCR Initialized — — — — — — — Initialized
PFNOCR Initialized — — — — — — — Initialized
PCNOCR Initialized — — — — — — — Initialized
PDNOCR Initialized — — — — — — — Initialized
PORT
TWR0MW — — — — — — — — — LPC
TWR0SW — — — — — — — — —
TWR1 — — — — — — — — —
TWR2 — — — — — — — — —
TWR3 — — — — — — — — —
TWR4 — — — — — — — — —
TWR5 — — — — — — — — —