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Rev. 1.00, 05/04, page 204 of 544
Table 10.4 Registers Accessible by TMR_X/TMR_Y
TMRX/Y H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7
0 TMR_X
TCR_X
TMR_X
TCSR_X
TMR_X
TICRR
TMR_X
TICRF
TMR_X
TCNT
TMR_X
TCORC
TMR_X
TCORA_X
TMR_X
TCORB_X
1 TMR_Y
TCR_Y
TMR_Y
TCSR_Y
TMR_Y
TCORA_Y
TMR_Y
TCORB_Y
TMR_Y
TCNT_Y
TMR_Y
TISR
10.3.11 Timer XY Control Register (TCRXY)
TCRXY selects the TMR_X and TMR_Y output pins and internal clock.
Bit Bit Name
Initial
Value
R/W Description
7 IOSX 0 R/W TMR_X I/O Select
0: Output to P67/TMOX and input from P60/TMIX
1: Output to PF6/ExTMOX and input from PF4/ExTMIX
6 IOSY 0 R/W TMR_Y Output Enable
0: Output to PF7/TMOY is prohibited and input from
P62/TMIY
1: Output to PF7/TMOY is permitted and input from
PF5/ExTMIY
5 CKSX 0 R/W TMR_X Clock Select
For details about selection, see the clock conditions in
table 10.3.
4 CKSY 0 R/W TMR_Y Clock Select
For details about selection, see the clock conditions in
table 10.3.
3 to 0 — All 0 R/W Reserved
The initial value should not be changed.
Note: * The program development tool (emulator) does not support TCRXY.