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Rev. 1.00, 05/04, page 78 of 544
5.5 Interrupt Exception Handling Vector Table
Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For
default priorities, the lower the vector number, the higher the priority. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt
requests from modules that are set to control level 1 (priority) by the ICR bit setting and the I and
UI bits in CCR are given priority and processed before interrupt requests from modules that are set
to control level 0 (no priority).
Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities
Vector Address
Origin of
Interrupt
Source
Name
Vector
Number
Normal
Mode
Advanced
Mode
ICR Priority
NMI 7 H'000E H'00001C — High
IRQ0 16 H'0020 H'000040 ICRA7
IRQ1 17 H'0022 H'000044 ICRA6
IRQ2
IRQ3
18
19
H'0024
H'0026
H'000048
H'00004C
ICRA5
IRQ4
IRQ5
20
21
H'0028
H'002A
H'000050
H'000054
ICRA4
External pin
IRQ6, KIN7 to KIN0
IRQ7, KIN15 to KIN8, WUE7 to
WUE0
22
23
H'002C
H'002E
H'000058
H'00005C
ICRA3
— Reserved for system use 24 H'0030 H'000060 —
WDT_0 WOVI0 (Interval timer) 25 H'0032 H'000064 ICRA1
WDT_1 WOVI1 (Interval timer) 26 H'0034 H'000068 ICRA0
— Address break 27 H'0036 H'00006C —
— Reserved for system use 28
to
47
H'0038
to
H'005E
H'000070
to
H'0000BC
—
FRT ICIA (Input capture A)
ICIB (Input capture B)
ICIC (Input capture C)
ICID (Input capture D)
OCIA (Output compare A)
OCIB (Output compare B)
FOVI (Overflow)
Reserved for system use
48
49
50
51
52
53
54
55
H'0060
H'0062
H'0064
H'0066
H'0068
H'006A
H'006C
H'006E
H'0000C0
H'0000C4
H'0000C8
H'0000CC
H'0000D0
H'0000D4
H'0000D8
H'0000DC
ICRB6
— Reserved for system use 56
to
63
H'0070
to
H'007E
H'0000E0
to
H'0000FC
—
Low