Filter
Top Products
Rev. 1.00, 05/04, page 212 of 544
10.7.3 Input Capture Operation
TMR_X has input capture registers (TICRR and TICRF). A narrow pulse width can be measured
with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMR_X input
capture input signal) is detected after its rising edge has been detected, the value of TCNT_X at
that time is transferred to both TICRR and TICRF.
10.8 TMR_B and TMR_A Cascaded Connection
If bits CKS2 to CKS0 in either TCR_B or TCR_A are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode
can be selected by the settings of the CKSA and CKSB bits in TCRAB.
10.8.1 16-Bit Count Mode
When bits CKS2 to CKS0 in TCR_B are set to B'100 and the CKSB bit in TCRAB is set to 1, the
timer functions as a single 16-bit timer with TMR_B occupying the upper eight bits and TMR_A
occupying the lower 8 bits.
Setting of compare-match flags
The CMF flag in TCSR_B is set to 1 when an upper 8-bit compare-match occurs.
The CMF flag in TCSR_A is set to 1 when a lower 8-bit compare-match occurs.
Counter clear specification
If the CCLR1 and CCLR0 bits in TCR_B have been set for counter clear at compare-match,
only the upper eight bits of TCNT_B are cleared. The upper eight bits of TCNT_B are also
cleared when counter clear by the TMRIB pin has been set.
The settings of the CCLR1 and CCLR0 bits in TCR_A are enabled, and the lower 8 bits of
TCNT_A can be cleared by the counter.
Pin output
Control of output from the TMOB pin by bits OS3 to OS0 in TCSR_B is in accordance with
the upper 8-bit compare-match conditions.
Control of output from the TMOA pin by bits OS3 to OS0 in TCSR_A is in accordance with
the lower 8-bit compare-match conditions.
10.8.2 Compare-Match Count Mode
When bits CKS2 to CKS0 in TCR_A are set to B'100 and the CKSA bit in TCRAB is set to 1,
TCNT_A counts the occurrence of compare-match A for TMR_B. TMR_A and TMR_B are
controlled independently. Conditions such as setting of the CMF flag, generation of interrupts,
output from the TMO pin, and counter clearing are in accordance with the settings for each
channel.