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Rev. 1.00, 05/04, page 463 of 544
Section 20 Power-Down Modes
For operating modes after the reset state is cancelled, this LSI has not only the normal program
execution state but also seven power-down modes in which power consumption is significantly
reduced. In addition, there is also module stop mode in which reduced power consumption can be
achieved by individually stopping on-chip peripheral modules.
• Medium-speed mode
System clock frequency for the CPU operation can be selected as φ/2, φ/4, φ/8, φ/16, or φ/32.
• Subactive mode
The CPU operates based on the subclock and on-chip peripheral modules other than TMR_0,
TMR_1, WDT_0, and WDT_1 stop operating.
• Sleep mode
The CPU stops but on-chip peripheral modules continue operating.
• Subsleep mode
The CPU and on-chip peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1
stop operating.
• Watch mode
The CPU and on-chip peripheral modules other than WDT_1 stop operating.
• Software standby mode
Clock oscillation stops, and the CPU and on-chip peripheral modules stop operating.
• Hardware standby mode
Clock oscillation stops, and the CPU and on-chip peripheral modules enter reset state.
• Module stop mode
Independently of above operating modes, on-chip peripheral modules that are not used can be
stopped individually.
20.1 Register Descriptions
Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR,
MSTPCRH, and MSTPCRL, the FLSHE bit in the serial timer control register (STCR) must be
cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register (STCR).
• Standby control register (SBYCR)
• Low power control register (LPWRCR)
• Module stop control register H (MSTPCRH)
• Module stop control register L (MSTPCRL)