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Rev. 1.00, 05/04, page 284 of 544
13.3.3 Second Slave Address Register (SARX)
SARX sets the second slave address and selects the communication format. If the LSI is in slave
mode with the I
2
C bus format selected, when the FSX bit is set to 0 and the upper 7 bits of SARX
match the upper 7 bits of the first frame received after a start condition, the LSI operates as the
slave device specified by the master device. SARX can be accessed only when the ICE bit in
ICCR is cleared to 0.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Second Slave Address 6 to 0
Set the second slave address.
0 FSX 1 R/W Format Select X
Selects the communication format together with the FS
bit in SAR. See table 13.2.