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Intel
®
IXP43X Product Line of Network Processors
April 2007 HDG
Document Number: 316844; Revision: 001US 29
Hardware Design Guidelines—Intel
®
IXP43X Product Line of Network Processors
3.5 MII Interface
The IXP43X network processors support a maximum of two Ethernet MACs. Depending
on the part number of the IXP43X network processors, various combinations can be
used. Refer to the Intel
®
IXP43X Product Line of Network Processors Datasheet for a
detailed list of features that can be enabled depending upon your requirements.
All MACs contained in the NPEs are compliant to the IEEE 802.3 specification and
handle flow control for the IEEE 802.3Q VLAN specification.
The Management Data Interface (MDI) supports a maximum of 32 PHY addresses. MDI
signals are required to be connected to every PHY chip. Each PHY port is assign a
unique address in the external PHY chip from 0 to 31, totaling a maximum of 32 PHY
addresses. The maximum number of MACs supported by the IXP43X network
processors is two.
The MII interface supports clock rates of 25 MHz for 100-Mbps operation or 2.5 MHz for
10-Mbps operation.
Figure 5. UART Interface Example
Intel® IXP43X
Product Line of
Network Processors
Intel® IXP43X
Product Line of
Network Processors
UART
Interface
DB9
Connector (Female)
CTS0_N
RTS0_N
RXDATA0
TXDATA0
OUT4
OUT1
RS-232
Transceiver
IN3
IN2
NC
IN1
IN4
OUT2
OUT3
1 DCD
2 RX
3 TX
4 DTR
5 GND
6 DSR
7 RTS
8 CTS
9 RI
1
6
2
7
3
8
4
9
5
B4099-005