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IXP43X Product Line of Network Processors—Hardware Design Guidelines
Intel
®
IXP43X Product Line of Network Processors
HDG April 2007
70 Document Number: 316844; Revision: 001US
6.3.2 Routing Guidelines
It is recommended to route signals with respect to an adjacent ground plane. If routing
signals over power planes, ensure that the signals are referenced to a single power
plane voltage level and not multiple levels. For example, you can route signals over a
3.3 V plane or a 5 V plane, but do not route the same signal over both planes. If signals
are routed over split planes, you must connect the splitting planes with 0.01 µF,
high-speed capacitors near the signal crossing the split. The capacitors should not be
placed more than 0.25 inches from the point at which the signals cross the split.
This manual does not repeat all the guidelines that are already stated in the
PCI Local Bus Specification, Rev. 2.2. Refer to the specification when designing a
motherboard or an expansion card.
6.3.3 Signal Loading
Shared PCI signals must be limited to one load on each of the PCI slots. Any violation of
expansion board or add-on device trace length or loading limits compromises
system-signal integrity.
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