Intel IXP43X Computer Hardware User Manual


 
Intel
®
IXP43X Product Line of Network Processors
April 2007 HDG
Document Number: 316844; Revision: 001US 9
Hardware Design Guidelines—Intel
®
IXP43X Product Line of Network Processors
1.0 Introduction
This design guide provides recommendations for hardware and system designers who
are developing with the Intel
®
IXP43X Product Line of Network Processors. This
document should be used in conjunction with the Intel
®
IXP43X Product Line of
Network Processors Datasheet and sample schematics provided for the Intel
®
IXP435
Multi-Service Residential Gateway Reference Platform.
Design recommendations are necessary to meet the timing and signal quality
specifications. The guidelines recommended in this document are based on experience
and simulation work done at Intel while developing the Intel
®
IXP435 Multi-Service
Residential Gateway Reference Platform. These recommendations are subject to
change.
Note: This document discusses all features supported on the IXP43X product line of network
processors. A subset of these features is supported by certain processors in the IXP43X
network processors, such as the Intel
®
IXP432 Network Processor. Refer to the Intel
®
IXP43X Product Line of Network Processors Datasheet for detailed information on
various features listed by processor.
1.1 Content Overview
Chapter Name Description
Chapter 1.0, “Introduction” Conventions used in this manual and related documentation
Chapter 2.0, “System Architecture” System architectural block diagram and system memory map
Chapter 3.0, “General Hardware Design
Considerations”
Graphical representation of most common peripheral interfaces
Chapter 4.0, “General PCB Guide” General PCB design practice and layer stack-up description
Chapter 5.0, “General Layout and Routing
Guide”
More specific layout and routing recommendations for board
designers
Chapter 6.0, “PCI Interface Design
Considerations”
Board-design recommendations when implementing PCI
interface
Chapter 7.0, “DDRII / DDRI SDRAM”
Board-design recommendations when implementing
DDRII/I memory interface