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Intel
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IXP43X Product Line of Network Processors—Hardware Design Guidelines
Intel
®
IXP43X Product Line of Network Processors
HDG April 2007
82 Document Number: 316844; Revision: 001US
7.3.3 Routing Guidelines
7.3.3.1 Clock Group
The clock signal group includes the differential clock pairs D_CK[2:0] / DDR_CK[2:0]
and D_CK_N[2:0] / DDR_CK_N[2:0].
Here are some tips on how to route the differential clock pairs:
• Ensure that DDR clocks are routed on a single internal layers, except for pin
escapes
• A ground plane must be adjacent to the layer where the signals are routed
• Minimize the number of vias used, but ensure that the same number of vias are
used in the positive and negative trace
• It is recommended that pin escape vias be located directly adjacent to the ball pads
on all clocks
• Traces must be routed for differential mode impedance of 120 Ω
• Surface layer routing should be minimized (top or bottom layers)
• It is recommended to perform pre- and post-layout simulation
A series resistance value in the 25- to 50-Ω range should be used as it adds minimal
propagation delay to the signal without adversely varying from the CLK plus DQ
propagation delay average. The appropriate value for termination resistance should be
verified through simulation for the specific topology.
Table 34 provides routing guidelines for signals within this group.
Command
D_MA0 / DDR_MA0 515.78 D_MA7 / DDR_MA7 438.95
D_MA1 / DDR_MA1 357.69 D_MA8 / DDR_MA8 394.65
D_MA2 / DDR_MA2 509.12 D_MA9 / DDR_MA9 429.78
D_MA3 / DDR_MA3 462.16
D_MA10 /
DDR_MA10
378.96
D_MA4 / DDR_MA4 444.71
D_MA11 /
DDR_MA11
418.37
D_MA5 / DDR_MA5 576.87
D_MA12 /
DDR_MA12
392.79
D_MA6 / DDR_MA6 513.40
D_MA13 /
DDR_MA13
433.55
D_BA0 / DDR_BA0 530.35 D_BA1 / DDR_BA1 535.27
D_RAS_N /
DDR_RAS_N
506.35
D_CAS_N /
DDR_CAS_N
477.26
D_WE_N /
DDR_WE_N
513.09
Table 33. Signal Package Lengths (Sheet 3 of 3)
Group Signal Name Length (mil) Signal Name Length (mil)