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IXP43X Product Line of Network Processors—Hardware Design Guidelines
Intel
®
IXP43X Product Line of Network Processors
HDG April 2007
58 Document Number: 316844; Revision: 001US
• Poor routing density
• Uncontrolled signal trace impedance
• Lack of power/ground planes, resulting in unacceptable crosstalk
• Relatively high-impedance power distribution circuitry, resulting in
noise on the power and ground rails
• High-speed circuits require multi-layer printed circuit boards:
— Advantages:
• Controlled-impedance traces
• Low-impedance power distribution
— Disadvantages:
• Higher cost
•More weight
• Manufactured by fewer vendors
• Symmetry is essential to keep the board stack-up symmetric about the center
This minimizes warping
• For best impedance control, have:
— No more than two signal layers between every power/ground plane pair
— No more than one embedded micro-strip layer under the top/bottom layers
• For best noise control, route adjacent layers orthogonally. Avoid layer-to-layer
parallelism
• Fabrication house must agree on design rules, including:
— Trace width, trace separation
— Drill/via sizes
• The distance between the signal layer and ground (or power) should be minimized
to reduce the loop area enclosed by the return current
— Use 0.7:1 ratio as a minimum.
For example: 5-mil traces, 7-mil prepreg thickness to adjacent power/ground.
Figure 17 and Figure 18 provides an example for a six-layer and eight-layer board. For
stripline (signals between planes), the stackup should be such that the signal line is
closer to one of the planes by a factor of five or more. Then the trace impedance is
controlled predominantly by the distance to the nearest plane.