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S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
108
Register 0x33 (EXTD=0): RPOP Interrupt Enable
Bit Type Function Default
Bit 7 R/W PSLE 0
Bit 6 R/W Reserved 0
Bit 5 R/W LOPE 0
Bit 4 R/W Reserved 0
Bit 3 R/W PAISE 0
Bit 2 R/W PRDIE 0
Bit 1 R/W BIPEE 0
Bit 0 R/W FEBEE 0
NOTE: To facilitate additional register mapping, shadow registers have been
added to registers 0x30, 0x31 and 0x33. These shadow registers are accessed in
the same way as the normal registers.
The EXTD (extend register) bit must be set in register 0x36 to allow switching
between accessing the normal registers and the shadow registers
This register allows interrupt generation to be enabled for path level alarm and
error events.
FEBEE:
The FEBEE bit is the interrupt enable for path FEBEs. When FEBEE is a
logic one, an interrupt is generated when a path FEBE is detected.
BIPEE:
The BIPEE bit is the interrupt enable for path BIP-8 errors. When BIPEE is a
logic one, an interrupt is generated when a B3 error is detected.
PRDIE:
The PRDIE bit is the interrupt enable for path RDI. When PRDIE is a logic
one, an interrupt is generated when the path RDI state changes.
PAISE:
The PAISE bit is the interrupt enable for path AIS. When PAISE is a logic one,
an interrupt is generated when the path AIS state changes.