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S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
205
free. An all-ones pattern indicates that the header contains an uncorrectable
error (if the HCSPASS bit in the RXCP Control Register is set to logic zero, the
all-ones pattern will never be passed in this structure). An alternating ones and
zeros pattern (0xAA) indicates that the header contained a correctable error. In
this case the header passed through the structure is the "corrected" header.
In the transmit direction, the HCS bit in the TXCP Control register determines
whether the HCS is calculated internally or is inserted directly from the upper 8
bits of Word 3. The lower 8 bits of Word 3 contain the HCS control octet. The
HCS control octet is an error mask that allows the insertion of one or more errors
in the HCS octet. A logic one in a given bit position causes the inversion of the
corresponding HCS bit position (for example a logic one in bit 7 causes the most
significant bit of the HCS to be inverted).
13.3
Bit Error Rate Monitor
The S/UN-QUAD provides two BERM blocks. One can be dedicated to monitor at
the Signal Degrade (SD) error rate and the other dedicated to monitor at the
Signal Fail (SF) error rate.
The Bit Error Rate Monitor (BERM) block counts and monitor line BIP errors over
programmable periods of time (window size). It can monitor to declare an alarm
or to clear it if the alarm is already set. A different threshold and accumulation
period must be used to declare or clear the alarm, whether or not those two
operations are not performed at the same BER. The following table list the
recommended content of the BERM registers for different error rates (BER). Both
BERMs in the TSB are equivalent and are programmed similarly. In a normal
application they will be set to monitor different BER.
When the SF/SD CMODE bit is 1 this indicates that the clearing monitoring is
recommended to be performed using a window size that is 8 times longer than
the declaration window size. When the SF/SD CMODE bit is 0 this indicates that
the clearing monitoring is recommended to be performed using a window size
equal to the declaration window size. In all cases the clearing threshold is
calculated for a BER that is 10 times lower than the declaration BER, as required
in the references. The table indicates the declare BER and evaluation period only.
The Saturation threshold is not listed in the table, and should be programmed
with the value 0xFFF by default, deactivating saturation. Saturation capabilities
are provided to allow the user to address issues associated with error bursts.