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S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
51
10.11.3
HCS Generator
The HCS Generator performs a CRC-8 calculation over the first four header
octets. A parallel implementation of the polynomial, x
8
+x
2
+x+1, is used. The
coset polynomial, x
6
+x
4
+x
2
+1, is added (modulo 2) to the residue. The HCS
Generator optionally inserts the result into the fifth octet of the header.
10.12
UTOPIA Level 2 System Interface
The S/UNI-QUAD system interface provides a Utopia level 2 compliant bus to
transfer ATM cells between the ATM layer device and the S/UNI-QUAD.
10.12.1
Receive ATM Interface
The Receive ATM FIFO (RXCP) provides FIFO management at the S/UNI-QUAD
receive cell interface. The receive FIFO contains four cells. The FIFO provides
the cell rate decoupling function between the transmission system physical layer
and the ATM layer.
In general, the management functions include filling the receive FIFO, indicating
when the receive FIFO contains cells, maintaining the receive FIFO read and
write pointers, and detecting FIFO overrun and underrun conditions.
The FIFO interface is “UTOPIA Level 2" compliant and accepts a read clock
(RFCLK) and read enable signal (RENB). The receive FIFO output bus
(RDAT[15:0]) is tri-stated when RENB is logic one or if the PHY device address
(RADR[4:0]) selected does not match this device's address. The interface
indicates the start of a cell (RSOC) and the receive cell available status (RCA
and DRCA[4:1]) when data is read from the receive FIFO (using the rising edges
of RFCLK). The RCA (and DRCA[x]) status changes from available to
unavailable when the FIFO is either empty (RCALEVEL0=1) or near empty
(RCALEVEL0 is logic zero). This interface also indicates FIFO overruns via a
maskable interrupt and register bits. Read accesses while RCA (or DRCA[x]) is a
logic zero will output invalid data. The FIFO is reset on FIFO overrun, causing up
to 4 cells to be lost.
10.12.2
Transmit ATM Interface
The ATM Transmit FIFO (TXCP) provides FIFO management at the S/UNI-QUAD
transmit cell interface. The transmit FIFO contains four cells. The FIFO depth
may be programmed to four, three, two, or one cells. The FIFO provides the cell