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PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
36
codes are compared with the BIP-8 codes extracted from the following frame. Any
differences indicate that a line layer bit error has occurred. Optionally the RLOP
can be configured to count a maximum of only one BIP error per frame.
This block also extracts the line FEBE code from the third Z2 byte. The FEBE
code is contained in bits 2 to 8 of the Z2 byte, and represents the number of line
BIP-8 errors that were detected in the last frame by the far end. The FEBE code
value has 25 legal values (0 to 24) for an STS-3c (STM-1) stream. Illegal values
are interpreted as zero errors.
The Error Monitor Block accumulates B2 error events and FEBE events in two 20
bit saturating counter that can be read via the microprocessor interface. The
contents of these counters may be transferred to internal holding registers by
writing to any one of the counter addresses, or by using the TIP register bit
feature. During a transfer, the counter value is latched and the counter is reset to
0 (or 1, if there is an outstanding event). Note, these counters should be polled at
least once per second to avoid saturation.
The B2 error events counters optionally can be configured to accumulate only
"word" errors. A B2 word error is defined as the occurrence of one or more B2 bit
error events during a frame. The B2 error counter is incremented by one for each
frame in which a B2 word error occurs.
In addition the FEBE events counters optionally can be configured to accumulate
only "word" events. In STS-3c (STM-1) framing a FEBE word event is defined as
the occurrence of one or more FEBE bit events during a frame. The FEBE event
counter is incremented by one for each frame in which a FEBE event occurs.
10.4
The Receive APS, Synchronization Extractor and Bit Error Monitor (RASE)
10.4.1
Automatic Protection Switch Control
The Automatic Protection Switch (APS) control block filters and captures the
receive automatic protection switch channel bytes (K1 and K2) allowing them to
be read via the RASE APS K1 Register and the RASE APS K2 Register. The
bytes are filtered for three frames before being written to these registers. A
protection switching byte failure alarm is declared when twelve successive
frames have been received, where no three consecutive frames contain identical
K1 bytes. The protection switching byte failure alarm is removed upon detection
of three consecutive frames containing identical K1 bytes. The detection of
invalid APS codes is done in software by polling the RASE APS K1 Register and
the RASE APS K2 Register.