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S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
37
10.4.2
Bit Error Rate Monitor
The Bit Error Monitor Block (BERM) calculates the received line BIP-24 error
detection code (B2) based on the line overhead and synchronous payload
envelope of the receive data stream. The line BIP-24 code is a bit interleaved
parity calculation using even parity. Details are provided in the references. The
calculated BIP code is compared with the BIP-24 code extracted from the B2
byte(s) of the following frame. Any differences indicate that a line layer bit error
has occurred. Up to 192000 (24 BIP/frame x 8000 frames/second) bit errors can
be detected per second for STS-3c (STM-1) rate.
The BERM accumulates these line layer bit errors in a 20 bit saturating counter
that can be read via the microprocessor interface. During a read, the counter
value is latched and the counter is reset to 0 (or 1, if there is an outstanding
event). Note, this counter should be polled at least once per second to avoid
saturation which in turn may result in missed bit error events.
The BERM block is able to simultaneously monitor for signal fail (SF) or signal
degrade (SD) threshold crossing and provide alarms through software interrupts.
The bit error rates associated with the SF or SD alarms are programmable over a
range of 10
-3
to 10
-9
. Details are provided in the Operations section.
In both declaring and clearing detection states, the accumulated BIP count is
continuously compared against the threshold. This allows to rapidly declare in the
presence of error bursts or error rates that significantly exceed the monitored
BER. This behavior allows meeting the ITU-T G.783 detection requirements at
various error rates (where the detection time is a function of the actual BER, for a
given monitored BER.
10.4.3
Synchronization Status Extraction
The Synchronization Status Extraction (SSE) Block extracts the synchronization
status (S1) byte from the line overhead. The SSE block can be configured to
capture the S1 nibble after three or after eight frames with the same value
(filtering turned on) or after any change in the value (filtering turned off). The S1
nibble can be read via the microprocessor interface.
Optionally, the SSE can be configured to perform filtering based on the whole S1
byte. Although this mode of operation is not standard, it might become useful in
the future.