PMC-Sierra PM5349 Network Router User Manual


 
S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-SIERRA, Inc., and for its Customers’ Internal Use
I
CONTENTS
1 FEATURES ........................................................................................................................1
1.1 GENERAL.............................................................................................................1
1.2 THE SONET RECEIVER......................................................................................1
1.3 THE RECEIVE ATM PROCESSOR......................................................................2
1.4 THE SONET TRANSMITTER...............................................................................2
1.5 THE TRANSMIT ATM PROCESSOR ...................................................................3
2 APPLICATIONS .................................................................................................................4
3 REFERENCES ..................................................................................................................5
4 DEFINITIONS ....................................................................................................................6
5 APPLICATION EXAMPLES ...............................................................................................7
6 BLOCK DIAGRAM.............................................................................................................8
7 DESCRIPTION ..................................................................................................................9
8 PIN DIAGRAM .................................................................................................................11
9 PIN DESCRIPTION .........................................................................................................12
9.1 LINE SIDE INTERFACE SIGNALS ....................................................................12
9.2 UTOPIA LEVEL 2 SYSTEM INTERFACE ..........................................................15
9.3 MICROPROCESSOR INTERFACE SIGNALS ...................................................23
9.4 JTAG TEST ACCESS PORT (TAP) SIGNALS....................................................25
9.5 ANALOG SIGNALS ............................................................................................26
9.6 POWER AND GROUND.....................................................................................26
10 FUNCTIONAL DESCRIPTION ........................................................................................32
10.1 RECEIVE LINE INTERFACE (CRSI)..................................................................32
10.1.1 CLOCK RECOVERY.......................................................................32
10.1.2 SERIAL TO PARALLEL CONVERTER ...........................................33
10.2 RECEIVE SECTION OVERHEAD PROCESSOR (RSOP) ................................33
10.2.1 FRAMER .........................................................................................33
10.2.2 DESCRAMBLE................................................................................34
10.2.3 ERROR MONITOR..........................................................................34
10.2.4 LOSS OF SIGNAL ..........................................................................34
10.2.5 LOSS OF FRAME...........................................................................35