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S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
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rate decoupling function between the transmission system physical layer and the
ATM layer.
In general, the management functions include emptying cells from the transmit
FIFO, indicating when the transmit FIFO is full, maintaining the transmit FIFO
read and write pointers, and detecting a FIFO overrun condition.
The FIFO interface is “UTOPIA Level 2” compliant and accepts a write clock
(TFCLK), a write enable signal (TENB), the start of a cell (TSOC) indication, the
parity bit (TPRTY), and the ATM device address (TADR[4:0]) when data is written
to the transmit FIFO (using the rising edges of TFCLK). The interface provides
the transmit cell available status (TCA and DTCA[4:1]) which can transition from
"available" to "unavailable" when the transmit FIFO is near full (when
TCALEVEL0 is logic zero) or when the FIFO is full (when TCALEVEL0 is logic
one) and can accept no more writes. To reduce FIFO latency, the FIFO depth at
which TCA and DTCA[x] indicates "full" can be set to one, two, three or four cells
by the FIFODP[1:0] bits of TXCP Configuration 2 register. If the programmed
depth is less than four, more than one cell may be written after TCA or DTCA[x] is
asserted as the TXCP still allows four cells to be stored in its FIFO. This interface
also indicates FIFO overruns via a maskable interrupt and register bit, but write
accesses while TCA or DTCA[x] is logic zero are not processed. The TXCP
automatically transmits idle cells until a full cell is available to be transmitted.
10.13
JTAG Test Access Port
The JTAG Test Access Port block provides JTAG support for boundary scan. The
standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST
instructions are supported. The S/UNI-QUAD identification code is 053490CD
hexadecimal.
10.14
Microprocessor Interface
The microprocessor interface block provides normal and test mode registers, and
the logic required to connect to the microprocessor interface. The normal mode
registers are required for normal operation, and test mode registers are used to
enhance the testability of the S/UNI-QUAD. The register set is accessed as
shown in Table 3. In the following section every register is documented and
identified using the register number (REG #). The corresponding memory map
address for every channel (CH #1,2,3,4) is given in the table. Addresses that are
not shown are not used and must be treated as Reserved.
Table 3: Register Memory Map
Address A[10:0] Description