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S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
78
hundred milliseconds after the removal of the power on reset as the CRU PLL
locks to the receive reference clock.
RDOOLI:
The RDOOLI bit is the receive data out of lock interrupt status bit. RDOOLI is
set high when the RDOOLV bit of the S/UNI-QUAD Clock Recovery Control
and Status register changes state. RDOOLI is cleared when this register is
read.
RROOLI:
The RROOLI bit is the receive reference out of lock interrupt status bit.
RROOLI is set high when the RROOLV bit of the Clock Synthesis Control and
Status register changes state. RROOLI is cleared when this register is read.
Reserved:
The reserved bits must be programmed to logic zero for proper operation.