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47
intrinsic jitter is typically less than 0.01 UI RMS when measured using a high
pass filter with a 12 kHz cutoff frequency.
The REFCLK reference should be within ±20 ppm to meet the SONET free-run
accuracy requirements specified in GR-253-CORE.
10.7.2
Parallel to Serial Converter
The Parallel to Serial Converter (PISO) converts the transmit byte serial stream
to a bit serial stream. Every self-timed channel (a self-timed channel is one that
uses the CSU output clock) share a common line rate clock and byte clock, which
can be output as TCLK. Only self-timed channels can be synchronized using the
TFPI input. When a channel is loop-timed, TCLK, TFPI and TFPI are no more
available and the receive signals shall be used instead to extract timing
information.
10.8
Transmit Section Overhead Processor (TSOP)
The Transmit Section Overhead Processor (TSOP) provides frame pattern
insertion (A1, A2), scrambling, section level alarm signal insertion, and section
BIP-8 (B1) insertion.
10.8.1
Line AIS Insert
Line AIS insertion results in all bits of the SONET/SDH frame being set to 1
before scrambling except for the section overhead. The Line AIS Insert Block
substitutes all ones as described when enabled through an internal register (Reg
0x14, TSOP) accessed through the microprocessor interface. Activation or
deactivation of line AIS insertion is synchronized to frame boundaries.
10.8.2
BIP-8 Insert
The BIP-8 Insert Block calculates and inserts the BIP-8 error detection code (B1)
into the transmit stream.
The BIP-8 calculation is based on the scrambled data of the complete STS-3c
(STM-1) frame. The section BIP-8 code is based on a bit interleaved parity
calculation using even parity. Details are provided in the references. The
calculated BIP-8 code is then inserted into the B1 byte of the following frame
before scrambling. BIP-8 errors may be continuously inserted under register
control for diagnostic purposes.