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S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
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11
NORMAL MODE REGISTER DESCRIPTION
Normal mode registers are used to configure and monitor the operation of the
S/UNI-QUAD. Normal mode registers (as opposed to test mode registers) are
selected when TRS (A[10]) is low.
Notes on Normal Mode Register Bits:
1.
Writing values into unused register bits has no effect. However, to ensure
software compatibility with future, feature-enhanced versions of the product,
unused register bits must be written with logic zero. Reading back unused
bits can produce either a logic one or a logic zero; hence, unused register bits
should be masked off by software when read.
2.
All configuration bits that can be written into can also be read back. This
allows the processor controlling the S/UNI-QUAD to determine the
programming state of the block.
3.
Writable normal mode register bits are cleared to logic zero upon reset unless
otherwise noted.
4.
Writing into read-only normal mode register bit locations does not affect
S/UNI-QUAD operation unless otherwise noted. Performance monitoring
counters registers are a common exception.
5.
Certain register bits are reserved. These bits are associated with megacell
functions that are unused in this application. To ensure that the S/UNI-QUAD
operates as intended, reserved register bits must be written with their default
value as indicated by the register bit description.