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S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
232
Figure 25: Microprocessor Interface Write Timing
tH
DW
Valid Data
D[7:0]
tV
WR
tS
AW
tH
AW
tS
DW
(CSB+WRB)
A[10:0]
Valid Address
ALE
tV
L
tS
ALW
tS
LW
tH
ALW
tH
LW
Notes on Microprocessor Interface Write Timing:
1 A valid write cycle is defined as a logical OR of the CSB and the WRB
signals.
2 In non-multiplexed address/data bus architectures, ALE should be held high
so parameters tS
ALW
, tH
ALW
, tV
L
, tS
LW
, and tH
LW
are not applicable.
3 Parameter tH
AW
is not applicable if address latching is used.
4 When a set-up time is specified between an input and a clock, the set-up time
is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.
5 When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt
point of the clock.