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S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
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In normal operation, the HCS verification state machine remains in the
'Correction Mode' state. Incoming cells containing no HCS errors are passed to
the receive FIFO. Incoming single-bit errors are corrected, and the resulting cell
is passed to the FIFO. Upon detection of a single-bit error or a multi-bit error, the
state machine transitions to the 'Detection Mode' state. In this state,
programmable HCS error filtering is provided. The detection of any HCS error
causes the corresponding cell to be dropped. The state machine transitions back
to the 'Correction Mode' state when M (where M = 1, 2, 4, 8) cells are received
with correct HCSs. The Mth cell is not discarded.
10.6.4
Performance Monitor
The Performance Monitor consists of two 12-bit saturating HCS error event
counters and a 21-bit saturating receive cell counter. One of the counters
accumulates correctable HCS errors which are HCS single-bit errors detected
and corrected while the HCS Verification state machine is in the 'Correction
Mode' state. The second counter accumulates uncorrectable HCS errors which
are HCS bit errors detected while the HCS Verification state machine is in the
'Detection Mode' state or HCS bit errors detected but not corrected while the
state machine is in the 'Correction Mode' state. The 21-bit receive cell counter
counts all cells written into the receive FIFO. Filtered cells are not counted.
Each counter may be read through the microprocessor interface. Circuitry is
provided to latch these counters so that their values can be read while
simultaneously resetting the internal counters to 0 or 1, if appropriate, so that a
new period of accumulation can begin without loss of any events. It is intended
that the counter be polled at least once per second so as not to miss HCS error
events.
10.7
Transmit Line Interface (CSPI)
The Transmit Line Interface allows to directly interface the S/UNI-QUAD with
optical modules (ODLs) or other medium interfaces. This block performs clock
synthesis and performs parallel to serial conversion of the incoming outgoing
155.52 Mbit/s data stream.
10.7.1
Clock Synthesis
The transmit clock is synthesized from a 19.44 MHz reference. The transfer
function yields a typical low pass corner of 2.0 MHz above which reference jitter
is attenuated at 12 dB per octave. The design of the loop filter and PLL is
optimized for minimum intrinsic jitter. With a jitter free 19.44 MHz reference, the