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PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
219
otherwise be coupled into the analog circuitry. Current limiting can be
accomplished by using an off chip three terminal voltage regulator supplied
by a quiet high voltage supply. If the VDD power supply is relatively quiet,
VDD can be filtered using a ferrite bead and a high frequency decoupling
capacitor to supply AVD. The relative power sequencing of the multiple
AVD power supplies is not important.
5.) Power down the device in the reverse sequence. Use the above current
limiting technique for the analog power supplies. Small offsets in VDD /
AVD discharge times will not damage the device.
Figure 19 illustrates a power sequencing circuit to avoid latch-up or damage to
3.3V devices that are 5V tolerant. This circuit will ensure V
bias
is greater than V
dd
and protect against designs which require the 3.3V power supply appearing
before the 5V supply.
Figure 19: Power Sequencing Circuit
1K
Ω
3.3V
5V
0.1
µ
F
V
bias
Schottky
Diode
V
dd
13.9
Analog Power Supply Filtering
The noise environment and signal integrity are often the limiting factors of the
system performance, thus the following analog power filtering scheme is
recommended.