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S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-SIERRA, Inc., and for its Customers’ Internal Use
III
10.10.1 POINTER GENERATOR.................................................................49
10.10.2 BIP-8 CALCULATE..........................................................................50
10.10.3 FEBE CALCULATE.........................................................................50
10.11 TRANSMIT ATM CELL PROCESSOR (TXCP) ..................................................50
10.11.1 IDLE/UNASSIGNED CELL GENERATOR......................................50
10.11.2 SCRAMBLER..................................................................................50
10.11.3 HCS GENERATOR..........................................................................51
10.12 UTOPIA LEVEL 2 SYSTEM INTERFACE ..........................................................51
10.12.1 RECEIVE ATM INTERFACE ...........................................................51
10.12.2 TRANSMIT ATM INTERFACE.........................................................51
10.13 JTAG TEST ACCESS PORT...............................................................................52
10.14 MICROPROCESSOR INTERFACE....................................................................52
11 NORMAL MODE REGISTER DESCRIPTION ................................................................59
12 TEST FEATURES DESCRIPTION ................................................................................193
12.1 MASTER TEST REGISTER .............................................................................193
12.2 TEST MODE 0 DETAILS..................................................................................195
12.3 JTAG TEST PORT ............................................................................................196
12.3.1 BOUNDARY SCAN CELLS...........................................................198
13 OPERATION ..................................................................................................................201
13.1 SONET/SDH FRAME MAPPINGS AND OVERHEAD BYTE USAGE .............201
13.1.1 ATM MAPPING..............................................................................201
13.1.2 TRANSPORT AND PATH OVERHEAD BYTES............................202
13.2 ATM CELL DATA STRUCTURE ........................................................................204
13.3 BIT ERROR RATE MONITOR ..........................................................................205
13.4 CLOCKING OPTIONS......................................................................................206
13.5 LOOPBACK OPERATION ................................................................................208
13.6 JTAG SUPPORT...............................................................................................212
13.6.1 TAP CONTROLLER ......................................................................213
13.6.1.1 STATES ............................................................................215
13.6.1.2 INSTRUCTIONS ..............................................................216
13.7 BOARD DESIGN RECOMMENDATIONS ........................................................217
13.8 POWER SUPPLY SEQUENCING ....................................................................218