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S/UNI-QUAD
PMC-Sierra, Inc.
PM5349 S/UNI-QUAD
DATASHEET
PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
218
5.
The high speed serial streams (TXD+/- and RXD+/) must be routed with
controlled impedance circuit board traces and must be terminated with a
matched load. Normal CMOS-type design rules are not recommended and
will reduce the performance of the device.
13.8
Power Supply Sequencing
Due to ESD protection structures in the pads it is necessary to exercise caution
when powering a device up or down. ESD protection devices behave as diodes
between power supply pins and from I/O pins to power supply pins. Under
extreme conditions it is possible to blow these ESD protection devices or trigger
latch up. The recommended power supply sequencing follows:
1.) To prevent damage to the ESD protection on the device inputs the
maximum DC input current specification must be respected. This is
accomplished by either ensuring that the VDD power is applied before input
pins are driven or by increasing the source impedance of the driver so that
the maximum driver short circuit current is less than the maximum DC input
current specification. (20 mA)
2.) QAVD power must be supplied either after VDD or simultaneously with VDD
to prevent current flow through the ESD protection devices which exist
between QAVD and VDD power supplies. To prevent forward biasing the
ESD protection diode between QAVD supplies and VDD the differential
voltage measured between these power supplies must be less than 0.5 volt.
This recommended differential voltage is to include peak to peak noise on
the VDD power supply as digital noise will otherwise be coupled into the
analog circuitry. Current limiting can be accomplished by using an off chip
three terminal voltage regulator supplied by a quiet high voltage supply.
3.) BIAS voltage must be supplied either before VDD or simultaneously with
VDD to prevent current flow through the ESD protection devices which exist
between BIAS and VDD power supplies.
4.)
Analog power supplies (AVD, includes RAVDs, TAVDs but not QAVD)
should be applied after QAVD, but can be applied at the same time as
QAVD providing the 100ohm resistor in series with QAVD (shown in Figure
29 and Figure 30) is in place. The AVD supplies should also be current
limited to the maximum latchup current specification (100 mA). To prevent
forward biasing the ESD protection diode between AVD supplies and QAVD
the differential voltage measured between these power supplies must be
less than 0.5 volt. This recommended differential voltage is to include peak
to peak noise on the QAVD and AVD power supplies as digital noise will