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Register Descriptions Chapter 4
VXI-MXI User Manual 4-44 © National Instruments Corporation
3w ETRIG Enable Trigger Lines Bit
When this bit is set, the protocols selected by the OMS[2-0] bits
are enabled to drive the trigger line specified by the OTS[3-0] bits.
2r TRIGOUT Trigger Output Status Bit
If this bit is set, the trigger signal routed to the Trigger Out SMB
connector on the front panel is high. If this bit is cleared, that
trigger signal is low.
1r ASINT* Asynchronous Interrupt Status Bit
If this bit is set, the trigger signal selected by the ITS[3-0] bits is
monitored and, when the signal changes from unasserted to
asserted (high to low), an interrupt request is generated and this bit
is cleared. ASINT* is set again by writing to the Trigger
Asynchronous Acknowledge Register. In terms of the
asynchronous protocol, this bit is cleared after the acceptor has sent
an acknowledge by asserting the selected trigger line.
1w ASIE Asynchronous Interrupt Enable Bit
When this bit is set, an interrupt request is generated when the
trigger line selected by the ITS[3-0] bits changes from unasserted
to asserted (high to low).
0r SSINT* Synchronous Interrupt Status Bit
If this bit is set, the trigger signal selected by the ITS[3-0] bits is
monitored and, when the signal changes from asserted to
unasserted (low to high), an interrupt request is generated and this
bit is cleared. This bit is set again by writing to the Trigger
Synchronous Acknowledge Register. In terms of the semi-
synchronous protocol, this bit is cleared after all the acceptors have
unasserted the trigger line.
0w SSIE Synchronous Interrupt Enable Bit
When this bit is set, an interrupt request is generated when the
trigger line selected by the ITS[3-0] bits changes from asserted to
unasserted (low to high).