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Theory of Operation Chapter 6
VXI-MXI User Manual 6-2 © National Instruments Corporation
VMEbus Control Signals Transceivers
The VMEbus control signals transceivers control the sending and receiving of the VMEbus
control signals such as address strobe (AS*), the data strobes (DS1*, DS0*), longword
(LWORD*), write (WRITE*), data transfer acknowledge (DTACK*), and bus error (BERR*).
These signals indicate the beginning and end of a transfer, the size of data involved in the
transfer (8, 16 or 32 bits), whether the transfer is a read or a write, and whether or not the transfer
was successful.
VMEbus Requester and Arbiter Circuitry
Through the VMEbus requester and arbiter circuitry, a remote MXIbus device can access main
memory in the VXIbus system via the VMEbus. The arbiter circuitry is active on the VXI-MXI
only if the VXI-MXI is configured as the VXI Slot 0 device.
The VXI-MXI requests use of the VMEbus when it detects a MXIbus address that maps through
one of the mapping windows to the VMEbus. The VXI-MXI drives its VMEbus request line
active to initiate arbitration for the VMEbus. When the VXI-MXI is the highest priority
requesting device, it receives a bus grant signal indicating that the VMEbus is granted to the
VXI-MXI. The VXI-MXI drives the VMEbus BBSY* signal indicating that it owns the
VMEbus, and then releases its bus request line.
A remote MXIbus device can lock the VMEbus so that it can perform indivisible operations
across the VMEbus. When the LOCK bit in the Local Bus Lock Register is set by a MXIbus
device, the VXI-MXI interface will not release the VMEbus once it is granted the bus (on the
next transaction) until the LOCK bit is cleared by a MXIbus device.
TTL and ECL Trigger Lines and CLK10 Circuitry
The VXIbus TTL trigger lines (TTLTRG[7–0]), ECL trigger lines (ECLTRG[1-0]), and CLK10
circuitry provide triggering and synchronization for intermodule and interchassis communication.
For connecting trigger lines and clock signals between mainframes, the VXI-MXI front panel has
a TRG IN (Trigger In), a TRG OUT (Trigger Out), and an EXT CLK (External Clock) SMB
connector. Trigger lines can be mapped out of the VXIbus or routed into the mainframes via the
TRG OUT and TRG IN front panel connectors so that VXIbus devices in one mainframe can be
configured to trigger devices in other mainframes. By writing to the MXIbus Trigger
Configuration Register, individual VXIbus trigger lines can be selectively driven from the TRG
IN SMB connector or sourced to the TRG OUT SMB connector.
Using the Trigger Mode Selection Register and/or the Drive Triggers Register, the VXI-MXI can
source and/or accept Asynchronous, Synchronous, Semi-synchronous, and Start/Stop trigger
protocols, defined by the VXIbus specification, on any TTL or ECL Trigger Line. The
VXI-MXI can be configured to generate an interrupt on the rising and/or falling edge of any
trigger signal. This interrupt can be used to receive trigger protocols.
The Asynchronous protocol uses two trigger lines to communicate between a single source and a
single acceptor. The source device initiates the operation by asserting the lower-numbered
trigger line. The acceptor acknowledges by asserting the higher-numbered trigger line.