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VXI-MXI User Manual Index-6 © National Instruments Corporation
connector description, D-1 to D-2
definition, 1-4
limit for daisy-chained devices, 3-29
mapping, 1-4
signal assignments, D-1
signal groupings, D-2
system power cycling requirements, 3-30
to 3-31
termination networks, 3-24 to 3-25
MXIbus defined registers
configuration registers, 2-7, 6-6
Drive Triggers/Read LA Register, 4-39
to 4-40, 6-2
Interrupt Status/Control Register, 4-45
to 4-47
IRQ Acknowledge Registers, 4-51
MXIbus IRQ Configuration Register,
4-37 to 4-38
MXIbus Lock Register, 4-36
MXIbus Status/Control Register, 4-31
to 4-35
MXIbus Trigger Configuration Register,
4-49
Status/ID Register, 4-48, 6-4
Trigger Asynchronous Acknowledge
Register, 4-50
Trigger Mode Selection Register, 4-41
to 4-44, 6-2
Trigger Synchronous Acknowledge
Register, 4-50
MXIbus fairness option, configuration, 3-17
MXIbus IRQ Configuration Register, 4-37
to 4-38
MXIbus Lock Register, 4-36
MXIbus master mode state machine
deadlock situation, 6-10
definition, 2-7
master to slave transfers, 6-7
theory of operation, 6-6 to 6-10
timing specifications, A-3
transfer responses for VMEbus address
modifiers, 6-8
VMEbus/MXIbus transfer size
comparison, 6-9
VMEbus to MXIbus address modifier
line map, 6-7
MXIbus requester and arbiter circuitry
definition, 2-7
theory of operation, 6-12 to 6-14
MXIbus slave mode state machine
definition, 2-7
theory of operation, 6-10 to 11
timing specifications, A-3
MXIbus Status/Control Register, 4-31
to 4-35
MXIbus System Controller
configuration, 3-14 to 3-15
definition, 2-6
theory of operation, 6-12
timeout configuration, 3-16
MXIbus system logical address map
configuration. See logical address map
configuration.
MXIbus transceivers
address/data and address modifier
transceivers, 2-7, 6-11 to 6-12
control signal transceivers, 2-7, 6-12
requirements, 2-2
MXIbus Trigger Configuration
Register, 4-49
MXISC bit, 4-34
MXSCTO bit, 4-32
MXSRSTEN bit, 4-34
MXSRSTINT bit, 4-34
MXSYSFINT bit, 4-35
MXTRIGEN bit, 4-34
MXTRIGINT bit, 4-34
N
non-Slot 0 selection, 3-5
O
OMS[2-0] bits, 4-41 to 4-42
operation of VXI-MXI. See theory of
operation.
OTS[3-0] bits, 4-43
OUTEN bits, 4-9
P
PARERR bit, 4-35
parity check and generation, 2-7, 6-6
PASS bit, 4-8
physical specifications, A-3
pin assignments. See connector descriptions.
power cycling requirements, 3-30 to 3-31
programming. See logical address map
configuration; multiframe RM operation.
PULSE bit, 4-39