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Theory of Operation Chapter 6
VXI-MXI User Manual 6-6 © National Instruments Corporation
The VMEbus interrupt lines can be individually driven by writing to the Interrupt Status/Control
Register. When one of these interrupt requests is serviced by an interrupt handler, the
information in the Status/ID Register is returned during the IACK cycle and the interrupt request
is cleared.
Parity Check and Generation
All MXIbus devices are required to generate even parity. The VXI-MXI always generates and
checks parity on all 32 MXIbus address and data lines. If upper bytes of the address or data are
not driven, these lines are pulled high by the MXIbus termination circuitry and do not affect the
parity generation.
A32, A24, A16, and LA Windows
Four addressing windows map in and out of the VXIbus mainframe. These windows represent
the three VMEbus address spaces (A32, A24, and the lower 48 KB of A16) plus a dedicated
window for mapping the VXIbus configuration space (the upper 16 KB of A16). For each
window, the range that maps into the mainframe from the MXIbus to the VXIbus is whatever is
left over from the window that maps out of the mainframe from the VXIbus to the MXIbus.
VXI-MXI configuration registers are used to program these windows to indicate which addresses
in each window are mapped onto the MXIbus.
VXI-MXI Configuration Registers
The VXI-MXI configuration registers are accessible from both the VXIbus and the MXIbus and
are used to configure the VXI-MXI. These registers are described in detail in Chapter 4, Register
Descriptions.
When the VXI-MXI interface decodes a VMEbus address specifying the configuration space on
the card, the least significant VMEbus address lines are used to specify the registers in
configuration space and the VMEbus operation does not need to request control of the MXIbus.
Similarly, when the VXI-MXI interface decodes a MXIbus address specifying configuration
space on the card, the least significant MXIbus address lines are used to specify the registers in
configuration space and the access does not need to request control of the VMEbus. Onboard
circuitry automatically arbitrates between the MXIbus and VMEbus for use of the dual-ported
configuration space and prevents deadlock conditions on configuration space accesses.
MXIbus Master Mode State Machine
The VXI-MXI continuously compares VMEbus addresses and address modifiers to the four
MXIbus addressing windows. When a VMEbus transfer involving an address corresponding to
one of the outward mapping windows is detected, the VXI-MXI begins arbitrating for the
MXIbus. The VXI-MXI can translate A32, A24, A16, D32, D16, and D08(EO) VMEbus
transfers into corresponding MXIbus master mode transfers.
When the VXI-MXI wins ownership of the MXIbus, a MXIbus cycle is initiated and the
VMEbus transfer is converted into a MXIbus transfer. The MXIbus address and address strobe
are sent, followed by the data (if the transfer is a write) and a data strobe. The transfer is