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Theory of Operation Chapter 6
VXI-MXI User Manual 6-12 © National Instruments Corporation
MXIbus specifies trapezoidal bus transceivers to reduce noise and crosstalk in the MXIbus
transmission system. These transceivers have open collector drivers that generate precise
trapezoidal waveforms with typical rise and fall times of 9 ns. The trapezoidal shape, due to the
constant rise and fall times, reduces noise coupling to adjacent lines. The receiver uses a low
pass filter to remove noise in conjunction with a high-speed comparator that differentiates the
trapezoidal-shaped signal from the noise.
MXIbus cables are matched impedance cables. Each MXIbus signal line is twisted with a
ground line and the impedance is controlled by the thickness of the insulation around the wires.
This impedance matching minimizes skew between signals because they travel down the cable at
the same speed. Signal reflections are also minimized because the signals travel through the
same impedance as they daisy-chain through multiple cables. Termination resistor networks are
placed at the first and last MXIbus devices to minimize reflections at the ends of the cable.
MXIbus System Controller Functions
An onboard slide switch sets whether or not the VXI-MXI interface board is the MXIbus System
Controller. If it is the system controller, the VXI-MXI must be the first device in the MXIbus
daisy-chain. Onboard arbitration circuitry transparently performs the MXIbus arbitration for the
MXIbus chain. If the VXI-MXI interface board is not the first device in the MXIbus daisy-chain,
it can still be configured as the MXIbus System Controller. However, any devices in the
MXIbus daisy-chain that are upstream from the MXIbus System Controller cannot be MXIbus
masters because they will never be granted control of the MXIbus.
The MXIbus System Controller is also responsible for the MXIbus system timeout. This
timeout, typically 100 ms, begins when a MXIbus data strobe is received and stops when a
MXIbus DTACK or BERR is detected. When the timeout expires, the MXIbus System
Controller sends a MXIbus BERR to clear the MXIbus system. The VXI-MXI powers up with
the MXIbus system timeout between 100 µs and 400 µs, enabling the system Resource Manager
to scan all logical addresses in a reasonable amount of time. When the Resource Manager has
finished scanning and configuring the MXIbus system, it should set the LNGMXSCTO bit in the
MXIbus Control Register. When this bit is set, the MXIbus system timeout will be between
100 ms and 400 ms, as recommended in the MXIbus specification.
MXIbus Control Signals Transceivers
The MXIbus control signal transceivers control the sending and receiving of the MXIbus control
signals address strobe (AS*), data strobe (DS*), transfer size (SIZE*), read/write (WR*), data
transfer acknowledge (DTACK*), bus error (BERR*), and parity (PAR*). These signals indicate
the beginning and end of a transfer, the size of data involved in the transfer (8, 16, or 32 bits),
whether the transfer is a read or write, and whether the transfer was successful.
MXIbus Requester and Arbiter Circuitry
The MXIbus requester and arbiter circuitry is used to request and grant the MXIbus to MXIbus
devices. The arbiter circuitry is only active on the VXI-MXI if it is configured as the MXIbus
System Controller.